The present invention relates to photomask making method and alignment method for use in an exposure process carried out to fabricate a semiconductor device, for example, and more particularly relates to measures to realize highly accurate alignment (or high alignment accuracy).
Naturally, the advancement or development of photolithography techniques greatly contributes to recent tremendous increase in density of semiconductor devices integrated together per chip. However, it has been getting difficult to attain required alignment accuracy because the design rule has lately been reduced drastically. For example, a KrF excimer laser diode (with a wavelength of 248 nm) was realized lately and devices are being mass-produced in compliance with the design rule of 0.25 μm. On the other hand, the alignment accuracy should be about one third to one fourth of the design rule. This is because the accuracy required must be smaller than the wavelength of a measuring radiation by about one order of magnitude. The advancement of the technology has been improving the mechanical accuracy little by little. However, the improvement of the mechanical accuracy has almost reached a physical or theoretical limit and it has become very difficult to attain the required accuracy.
FIGS. 8A through 8D schematically illustrate the planar layouts of overall pattern for a unit chip among the patterns formed on a known reference-layer-defining photomask, on-mask intended pattern region, on-mask alignment accuracy measuring region and on-mask alignment region, respectively. A mask for defining an isolation film pattern will be described as an example. A “reference layer” herein means a layer in which the pattern of a type of members that should underlie another type of members is defined. A “layer to be aligned” herein means a layer that includes the latter type of members to be aligned with the former type of members in the reference layer. In this example, a layer in which the isolation film pattern is defined will be referred to as a “reference layer”. A layer in which gate electrode (or gate line) members are included will be referred to as a “layer to be aligned”.
As shown in FIG. 8A, the unit chip region Rtpms of the reference-layer-defining photomask includes the on-mask intended pattern region 101, on-mask alignment accuracy measuring regions 102, and first and second on-mask alignment regions 103a and 103b. An isolation film pattern for transistors to be fabricated in the chip has been defined in the on-mask intended pattern region 101. The on-mask alignment accuracy measuring regions 102 are for use to measure the alignment accuracy. The first and second on-mask alignment regions 103a and 103b are for use to align this photomask with a layer-to-be-aligned-defining photomask.
As shown in FIG. 8B, the on-mask intended pattern region 101 includes an isolation film pattern 111 that has a width of 3.5 μm and a space of 3.5 μm, for example. As shown in FIG. 8C, each of the on-mask alignment accuracy measuring regions 102 includes an on-mask alignment accuracy measuring mark 112 that has planar sizes of 10 μm square. As shown in FIG. 8D, a first group of on-mask alignment marks 113a, which form a line-and-space pattern with a width of 4 μm, a length of 20 μm and a space of 4 μm, are arranged in the on-mask alignment region 103a. Although not shown, the second on-mask alignment region 103b includes a second group of on-mask alignment marks extending vertically to the first group of on-mask alignment marks 113a shown in FIG. 8D. The second group of on-mask alignment marks has the same size as that of the first group of on-mask alignment marks 113a. 
FIGS. 9A through 9D are respectively a plan view illustrating a unit chip region of a wafer on which a reference layer pattern has been defined using the reference-layer-defining photomask shown in FIGS. 8A through 8D, a cross-sectional view illustrating an on-wafer intended pattern region, a cross-sectional view illustrating an on-wafer alignment accuracy measuring region and a cross-sectional view illustrating an on-wafer alignment region. As shown in FIG. 9A, the unit chip region Rtpwf of the wafer includes the on-wafer intended pattern region 121, on-wafer alignment accuracy measuring regions 122, and first and second on-wafer alignment regions 123a and 123b. An isolation film pattern for transistors to be fabricated in the chip has been defined in the on-wafer intended pattern region 121. Each of the on-wafer alignment accuracy measuring regions 122 includes an alignment accuracy measuring mark for measuring the alignment accuracy. The first and second on-wafer alignment regions 123a and 123b include alignment marks that are necessary for the alignment with a layer-to-be-aligned pattern. As shown in FIG. 9B, an on-wafer intended pattern 132 has been defined in the on-wafer intended pattern region 121 on an Si wafer 120. The on-wafer intended pattern 132 is formed by an isolation film 131 and the wafer surface surrounded with the isolation film 131. As shown in FIG. 9C, an on-wafer alignment accuracy measuring mark 133 has been formed in each of the on-wafer alignment accuracy measuring regions 122 on the Si wafer 120. The on-wafer alignment accuracy measuring mark 133 is formed by the isolation film 131 and the wafer surface surrounded with the isolation film 131. And as shown in FIG. 9D, on-wafer alignment marks 134 have been formed in the first and second on-wafer alignment regions 123a and 123b on the Si wafer 120. The on-wafer alignment marks 134 are formed by the isolation film 131 and the wafer surface surrounded by the isolation film 131.
FIGS. 10A through 10D schematically illustrate the planar layouts of overall pattern for a unit chip among the paterns formed on a known layer-to-be-aligned-defining photomask, on-mask intended pattern region, on-mask alignment accuracy measuring region and on-mask alignment region, respectively.
As shown in FIG. 10A, the unit chip region Rtpms includes the intended pattern region 151, alignment accuracy measuring regions 152, and first and second alignment regions 153a and 153b. A gate electrode (or gate line) pattern for transistors to be fabricated in the chip has been defined in the intended pattern region 151. The alignment accuracy measuring regions 152 are for use to measure the alignment accuracy. The first and second alignment regions 153a and 153b are provided for the purpose of the alignment with a photomask that will be used in the next process step.
As shown in FIG. 10B, the intended pattern region 151 includes a gate electrode (polysilicon film) pattern 161 made up of multiple gate electrodes, which are arranged to have a width of 0.5 μm and a space of 0.5 μm, for example and each three of which will make a set. As shown in FIG. 10C, each of the alignment accuracy measuring regions 152 includes an alignment accuracy measuring mark 162 that has planar sizes of 5 μm square. And as shown in FIG. 10D, a first group of alignment marks 163a, which will make a reference layer pattern in the next process step and which forms a line-and-space pattern with a width of 4 μm, a length of 20 μm and a space of 4 μm, are arranged in the first alignment region 153a. Although not shown, the second alignment region 153b includes a second group of alignment marks extending vertically to the first group of alignment marks 163a. The second group of alignment marks forms a line-and-space pattern and has the same sizes as those of the first group of alignment marks 163a. 
FIGS. 11A through 11D are respectively a plan view illustrating a unit chip region of a wafer on which a layer-to-be-aligned pattern has been defined using the layer-to-be-aligned-defining photomask shown in FIGS. 10A through 10D, a cross-sectional view illustrating an on-wafer intended pattern region, a cross-sectional view illustrating an on-wafer alignment accuracy measuring region and a cross-sectional view illustrating an on-wafer alignment region.
As shown in FIG. 11A, the unit chip region Rtpwf of the wafer includes the on-wafer intended pattern region 171, on-wafer alignment accuracy measuring regions 172, and first and second on-wafer alignment regions 173a and 173b. An isolation film pattern for transistors to be fabricated in the chip has been defined in the on-wafer intended pattern region 171. Each of the on-wafer alignment accuracy measuring regions 172 includes an on-wafer alignment accuracy measuring mark for measuring the alignment accuracy. The first and second on-wafer alignment regions 173a and 173b include alignment marks that are necessary for the alignment with a photomask to be used in the next process step. As shown in FIGS. 11B through 11D, a polysilicon film 181 for forming gate electrodes and a masking photoresist film 182 for patterning the polysilicon film 181 have been formed on the intended pattern region of the Si wafer.
As shown in FIG. 11B, the on-wafer intended pattern 132 (gate pattern) has already been defined for the reference layer by the isolation film 131 and wafer surface in the on-wafer intended pattern region 171. An on-wafer intended pattern 183 is going to be formed for the layer-to-be-aligned on the on-wafer intended pattern 132 so that gate electrodes will be arranged three by three at a width of 0.5 μm and a space of 0.5 μm. For that purpose, the mask is automatically aligned by reference to the on-wafer alignment marks 134 for the reference layer shown in FIG. 9A. Thereafter, the photoresist film 182 is exposed and developed and thereby defining a resist pattern for forming the gate electrodes, alignment accuracy measuring marks (see the parts indicated by broken lines) and alignment marks for the next process step, for example.
Also as shown in FIG. 11C, each of the alignment accuracy measuring regions 172 has a box-in-box pattern with an outer frame of 10 μm square and an inner frame of 5 μm square. The box-in-box pattern is formed by the on-wafer alignment accuracy measuring mark 133 for the reference layer and a resist pattern 184 for the layer-to-be-aligned, which is formed inside the on-wafer alignment accuracy measuring mark 133. An alignment error (mask misalignment) between the gate electrode pattern (intended pattern) to be formed using this resist pattern and the pattern of the underlying isolation film 131, for example, can be read by the relative positional relationship between the outer and inner frames of the box-in-box pattern. This it to say, the alignment accuracy can be measured.
Furthermore, as shown in FIG. 11D, a resist pattern 185 for forming reference alignment marks (out of the polysilicon film 181) for use in the next alignment process step through patterning is defined in the resist film 182 for forming the gate electrodes for the layer-to-be-aligned.
If the alignment error exceeds a predetermined value, the photoresist film is removed, the relative positional relationship between the wafer and photomask is corrected and a resist pattern is defined all over again.
FIG. 12 is a cross-sectional view illustrating the shapes of aligner, photomask and wafer in an exposure process. Normally, a stepping demagnification projection aligner (stepper) is used for an exposure process in a photolithography process. Although an objective lens for the stepper is illustrated as a thin one in FIG. 12, the optical system actually used is a complicated combination of many lenses and mechanisms.
Suppose that a photoresist film for defining intended pattern, alignment accuracy measuring mark pattern and alignment mark pattern, for example, has already been formed on the wafer and that those patterns are classifiable into rough and fine patterns. Accordingly, rough and fine pattern regions for defining the rough and fine patterns have been formed on the photomask. The intended and alignment mark patterns are formed in the photoresist film on the wafer by allowing the light that has been transmitted through the photomask to pass through the objective lens. As a result, the latent images of the rough and fine patterns are formed in the photoresist film. When the photoresist film is developed, a resist pattern is formed. Thereafter, etching and other processes are performed using the resist pattern as a mask, thereby forming rough and fine pattern members (e.g., isolation film, gate electrodes, alignment accuracy measuring marks, and alignment marks) on the wafer.
If a demagnification projection alinger is used, a photomask has a pattern that is several times greater in size than a pattern to be defined on a wafer. However, in FIG. 12, the pattern on the photomask is shown as if the pattern on the photomask were of the same size as the pattern on the wafer for the sake of simplicity of description.
Generally speaking, objective lenses provided for the stepper needs to be almost ideal ones and are made by making full use of the cutting-edge technology. However, it is well known that the objective lenses actually cause some distortion or aberration. The aberration is roughly classifiable into the five types of: distortion; curvature of field; coma; spherical; and astigmatic aberrations. Among other things, the coma and spherical aberrations affect the alignment accuracy seriously.
It is also generally known that the coma and spherical aberrations have pattern size dependence, thus shifting the position of a pattern horizontally, i.e., causing a misalignment.
The coma and spherical aberrations have pattern size dependence. Accordingly, if a position on a wafer onto which a photomask pattern is transferred (resist pattern position) when there are no aberrations at all is regarded as an ideal position, a position on the wafer onto which the resist pattern is actually defined shifts from the ideal position to some extent. In that case, the diffraction of light affects the fine patterns more seriously than the rough patterns. Thus, the fine patterns tend to be misaligned more greatly than the rough patterns. This misalignment can be corrected by adjusting the space between adjacent objective lenses, the tilt angles of the lenses, and the air pressure (refractive index), for example. Anyway, the shift of a rough pattern from its ideal position is different from that of a fine pattern from its ideal position.
FIG. 13 is a view illustrating how the positions of gate electrodes shift due to the pattern dependence of the aberrations. Suppose the alignment marks can be read and the resist pattern or the gate electrode pattern can be formed with no errors in this example. In that case, since the aberrations have some pattern size dependence as described above, the isolation film pattern (line-and-apace pattern with a width of 3.5 μm) as an intended reference layer pattern as shown in FIG. 9B and the gate electrode pattern (line-and-apace pattern with a width of 0.5 μm) as an intended layer-to-be-aligned pattern as shown in FIG. 11B have mutually different relative positions by reference to the reference position of an alignment mark. As a result, supposing the distance between an isolation film edge and the reference position of the alignment mark is “x” and the ideal distance between an edge of a gate electrode and the isolation film edge is “y”, the distance of the edge of the gate electrode actually formed from the isolation film edge is greater than the ideal distance “y” by “Δy” due to the pattern size dependence of the aberration.
Similarly, the outer and inner frames of an alignment accuracy measuring mark pattern also have mutually different pattern sizes. Thus, the pattern size dependence makes the actual relative positional relationship between the outer and inner frames different from the intended one. Accordingly, the alignment accuracy might be read erroneously.
That is to say, the accuracy of the photolithographic process might be deteriorated due to the pattern size dependence of the coma and spherical aberrations. In other words, improvement in the mechanical accuracy of optical members for use in the photolithographic process might not result in sufficient improvement in the accuracy of the photolithographic process.